Timing Optimization Through Clock Skew Scheduling / Edition 1

Timing Optimization Through Clock Skew Scheduling / Edition 1

ISBN-10:
0387710558
ISBN-13:
9780387710556
Pub. Date:
11/21/2008
Publisher:
Springer US
ISBN-10:
0387710558
ISBN-13:
9780387710556
Pub. Date:
11/21/2008
Publisher:
Springer US
Timing Optimization Through Clock Skew Scheduling / Edition 1

Timing Optimization Through Clock Skew Scheduling / Edition 1

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Overview

History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe firstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers’ desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.

Product Details

ISBN-13: 9780387710556
Publisher: Springer US
Publication date: 11/21/2008
Edition description: 2009
Pages: 266
Product dimensions: 6.10(w) x 9.25(h) x 0.03(d)

Table of Contents

VLSI Systems.- Signal Delay in VLSI Systems.- Timing Properties of Synchronous Systems.- Clock Skew Scheduling and Clock Tree Synthesis.- Clock Skew Scheduling of Level-Sensitive Circuits.- Clock Skew Scheduling for Improved Reliability.- Delay Insertion and Clock Skew Scheduling.- Practical Considerations.- Clock Skew Scheduling in Rotary Clocking Technology.- Experimental Results.
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