The VHDL Handbook / Edition 1

by David R. Coelho

Overview

This book is intended to be a working reference for electronic hardware de­ signers who are interested in writing VHDL models. A handbook/cookbook approach is taken, with many complete examples used to illustrate the fea­ tures of the VHDL language and to provide insight into how particular classes of hardware devices can be modelled in VHDL. It is possible to use these models directly or to adapt them to similar problems with minimal effort. This book is not intended to be a complete reference manual for the VHDL language. It is possible to begin writing VHDL models with little background in VHDL by copying examples from the book and adapting them to particular problems. Some exposure to the VHDL language prior to using this book is recommended. The reader is assumed to have a solid hardware design background, preferably with some simulation experience. For the reader who is interested in getting a complete overview of the VHDL language, the following publications are recommended reading: • An Introduction to VHDL: Hardware Description and Design [LIP89] • IEEE Standard VHDL Language Reference Manual [IEEE87] • Chip-Level Behavioral Modelling [ARMS88] • Multi-Level Simulation of VLSI Systems [COEL87] Other references of interest are [USG88], [DOD88] and [CLSI87] Use of the Book If the reader is familiar with VHDL, the models described in chapters 3 through 7 can be applied directly to design problems.

Product Details

ISBN-13:	9780792390312
Publisher:	Springer US
Publication date:	06/30/1989
Edition description:	1989
Pages:	390
Product dimensions:	6.10(w) x 9.25(h) x 0.36(d)

Table of Contents

1 Introduction.- 1.1 Introduction to the VHDL Language.- 1.2 Multi-Level Design.- 1.3 The Model Accuracy Continuum.- 2 Anatomy of a VHDL Model.- 2.1 Describing Electronic Hardware in VHDL.- 2.2 A VHDL File.- 2.3 The Standard Logic Package.- 2.4 User Defined Packages.- 2.5 VHDL Models and the Accuracy Continuum.- 2.6 Handling Timing Using Configurations.- 2.7 Using VHDL as a Stimulus Language.- 2.8 Standardized VHDL Modelling Conventions.- 3 Combinational Devices.- 3.1 Simple Gates.- 3.2 Selectors/Multiplexers.- 3.3 Switch Level Devices.- 3.4 Simple ALU’s.- 3.5 One Shots.- 3.6 Comparators.- 3.7 Parity Generators/Checkers.- 4 Sequential Devices.- 4.1 Flip-Flops.- 4.2 Registers.- 4.3 Counters.- 5 Memory Devices.- 5.1 Memory Initialization.- 5.2 Read Only Memories.- 5.3 Random Access Memories.- 5.4 PALs, PLDs.- 6 Complex Devices.- 6.1 Getting Started.- 6.2 The Timing Model.- 6.3 Error Handling.- 6.4 Techniques for Modeling.- 6.5 Quality Assurance.- 7 The Standard Logic Package.- 7.1 Using the Standard Logic Package.- 7.2 The Logic Value System.- 7.3 Technology Rules.- 7.4 Bus Resolution.- 7.5 Logic Manipulation.- 7.6 Timing Utilities.- 7.7 Integer Data Utilities.

Editorial Reviews

A thorough, feature-by-feature introduction to VHDL. Contains the first full explanation of the IEEE 1976 standard for VHDL. Provides an understanding of VHDL as a language and as a design tool. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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