Security Policy in System-on-Chip Designs: Specification, Implementation and Verification available in Hardcover, eBook
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Security Policy in System-on-Chip Designs: Specification, Implementation and Verification
- ISBN-10:
- 3319934635
- ISBN-13:
- 9783319934631
- Pub. Date:
- 10/09/2018
- Publisher:
- Springer International Publishing
- ISBN-10:
- 3319934635
- ISBN-13:
- 9783319934631
- Pub. Date:
- 10/09/2018
- Publisher:
- Springer International Publishing
![Security Policy in System-on-Chip Designs: Specification, Implementation and Verification](http://vs-images.bn-web.com/static/redesign/srcs/images/grey-box.png?v11.13.3)
Security Policy in System-on-Chip Designs: Specification, Implementation and Verification
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Overview
• Provides comprehensive coverage of SoC security requirements, security policies, languages, and security architecture for current and emerging computing devices;
• Explodes myths and ambiguities in SoC security policy implementations, and provide a rigorous treatment of the subject;
• Demonstrates a rigorous, step-by-step approach to developing a diversity of SoC security policies;
• Introduces a rigorous, disciplined approach to “hardware patching”, i.e., secure technique for updating hardware functionality of computing devices in-field;
• Includes discussion of current and emerging approaches for security policy verification.
Product Details
ISBN-13: | 9783319934631 |
---|---|
Publisher: | Springer International Publishing |
Publication date: | 10/09/2018 |
Edition description: | 1st ed. 2019 |
Pages: | 116 |
Product dimensions: | 6.10(w) x 9.25(h) x (d) |
About the Author
Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a Preeminence Professor and Steven Yatauro Faculty Fellow in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder Associate Professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over 250 publications in peer-reviewed journals and premier conferences and four books (three edited) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptivenanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005) as a team member, best paper award in IEEE BioMedical Circuits and Systems Conference (BioCAS 2016), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009). Dr. Bhunia has been serving as founding editor-in-chief in Journal of Hardware and Systems Security (HaSS), an associate editor of IEEE Transactions on CAD (TCAD), IEEE Transactions on Multi-Scale Computing Systems (TMSCS), ACM Journal of Emerging Technologies (JETC), and Journal of Low Power Electronics (JOLPE). He has served as a guest editor of IEEE Design & Test of Computers (2010, 2013), IEEE Computer Magazine (2016), IEEE Transcation on CAD (2015), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014). He has served as co-program chair of IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the technical program committee of many top-tier international conferences on design automation and security. He is a senior member of IEEE.
Table of Contents
Chapter1: SoC Security Policies: The State of the Practice.- Chapter2: E-IIPS: A Centralized Policy Implementation Architecture.- Chapter3: Exploiting Design-for-Debug in SoC Security Policy Architecture.- Chapter4: Security Assurance in SoC in presence of Untrusted IP Blocks.- Chapter5: A Move Towards a Hardware Patch.- Chapter6: SoC Security Policy Verification.- Chapter7: SoC Security Policies: Summary and Future Directions.