Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques / Edition 1

by Wolfgang Kunz, Dominik Stoffel

Overview

Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques.
While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems.
Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material.
Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies.

Product Details

ISBN-13:	9780792399216
Publisher:	Springer US
Publication date:	06/30/1997
Series:	Frontiers in Electronic Testing , #9
Edition description:	1997
Pages:	230
Product dimensions:	6.14(w) x 9.21(h) x 0.02(d)

Table of Contents

1 Preliminaries.- 2 Combinational Atpg.- 3 Recursive Learning.- 4 AND/OR Reasoning Graphs.- 5 Logic Optimization.- 6 Logic Verification.- 7 Conclusions and Future Work.- References.

Editorial Reviews

Develops new methods for analyzing the logic function of a given circuit, describing an alternative approach to dealing with Boolean functions and their implementations as multi-level circuits. The approach promises to be useful for supplementing existing Boolean representations in cases where they fail. Also demonstrates the usefulness of testing techniques in logic synthesis. Describes basic algorithmic concepts in automatic test pattern generation, logic synthesis, and verification; elaborates their relationship; and provides example applications to various problems relating to computer-aided design. Annotation c. by Book News, Inc., Portland, Or.

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