Random Telegraph Signals in Semiconductor Devices

by Eddy Simoen

Overview

As semiconductor devices move to the nanoscale, random telegraph signals have become an issue of major concern to the semiconductor industry. This book aims to provide a comprehensive and up-to-date review of one of the most challenging issues facing the semiconductor industry, from the fundamentals of random telegraph signals to applied technology.

Product Details

ISBN-13:	9780750312738
Publisher:	Iop Publishing Ltd
Publication date:	12/24/2016
Pages:	242
Product dimensions:	7.29(w) x 10.46(h) x 0.72(d)

Table of Contents

Preface vii

Acknowledgments ix

Author biographies x

List of symbols xii

List of Greek symbols xvi

List of abbreviations xviii

1 Introduction 1-1

References 1-4

2 Random telegraph signal phenomenology 2-1

2.1 RTS time constants 2-2

2.1.1 The SRH framework 2-2

2.1.2 Trap energy, capture barrier and location from the SRH approach 2-8

2.1.3 Non-SRH behavior: Coulomb blockade effects 2-13

2.1.4 Tunneling transitions 2-18

2.2 RTS amplitude behavior 2-23

2.3 RTS in the gate current of a MOS device 2-27

2.4 RTS in the junction leakage current of a MOSFET 2-36

2.5 Multiple and complex RTS 2-39

References 2-42

3 RTS modeling, simulation and parameter extraction 3-1

3.1 Time constant modeling and simulation 3-1

3.2 Extraction trap position from RTS time constants 3-7

3.3 RTS amplitude modeling 3-16

3.4 Atomistic numerical modeling of the RTS amplitude 3-23

3.5 Novel measurement and analysis methods 3-29

3.6 Ab initio modeling of RTS in gate dielectrics 3-34

References 3-36

4 Impact device processing and scaling on RTS 4-1

4.1 Processing effects on RTS 4-1

4.2 RTS in fin-type architectures 4-9

4.3 Nanometric scaling aspects of RTS 4-11

4.3.1 Scaling trend RTS amplitude 4-11

4.3.2 Silicon GAA NWs 4-14

4.3.3 High-mobility channel materials 4-17

4.3.4 RTS in TFETs 4-19

4.4 RTS in 'beyond-silicon' devices 4-20

4.4.1 CNT FETs 4-20

4.4.2 Other advanced devices 4-25

References 4-26

5 Operational and reliability aspects of RTS 5-1

5.1 Switching AC operation of RTS 5-1

5.2 Impact of uniform and HC degradation 5-3

5.3 BTI and RTS: oxide trapping? 5-9

5.4 Statistical RTS measurement methods 5-16

5.5 Device and circuit simulation of dynamic variability 5-19

References 5-24

6 RTS in memory and imager circuits 6-1

6.1 RTS in flash and SRAM cells 6-1

6.2 RTS in DRAM and logic circuits 6-8

6.3 RTS in novel ReRAM and PCMs 6-10

6.4 RTS in CMOS imagers and CCDs 6-24

References 6-26

7 General conclusions 7-1