Digital Integrated Circuit Design / Edition 1

by Ken Martin

Overview

Working from the fundamentals of transistor-level design and building up to system-level considerations, Digital Integrated Circuit Design shows students with minimal background in electronics how to design state-of-the-art high performance digital integrated circuits. Ideal as an upper-level undergraduate text, it can also be used in first-year graduate courses and as a reference for practicing engineers.

Digital Integrated Circuit Design:
BL Presents transistor-level details first, building up to system considerations
BL Emphasizes CMOS technology but also includes in-depth explanations of designing in bipolar, BiCMOS, and GaAs technologies
BL Features modern, well-designed examples and problems
BL Covers important system-level considerations such as timing, pipelining, clock distribution, and system building blocks in detail
BL Discusses key elements of semiconductor physics, integrated circuit processing, transistor-level design, logic-level design, system-level design, testing, and more
BL Provides physical and intuitive explanations throughout
BL Emphasizes conceptual thinking and design methodology over detailed circuit analysis techniques

Product Details

ISBN-13:	9780195125849
Publisher:	Oxford University Press
Publication date:	09/30/1999
Series:	The ^AOxford Series in Electrical and Computer Engineering
Edition description:	New Edition
Pages:	560
Product dimensions:	9.30(w) x 7.50(h) x 1.30(d)

About the Author

University of Toronto

Table of Contents

Preface1. THE BASICS1.1. Simple NMOS Logic Gates1.2. Simple CMOS Logic Gates1.3. Computer Simulation1.4. Transfer Curves and Noise Margins1.5. Gate Delays and Rise and Fall Times1.6. Transient Response1.7. An RC Approximation to the Transient Response of a CMOS Inverter1.8. Summary1.9. Bibliography1.10. Problems2. PROCESSING, LAYOUT, AND RELATED ISSUES2.1. CMOS Processing2.2. Bipolar Processing2.3. CMOS Layout and Design Rules2.4. Advanced CMOS Processing2.5. Bibliography2.6. Problems3. INTEGRATED-CIRCUIT DEVICES AND MODELING3.1. Simplified Transistor Modeling3.2. Semiconductors and pn Junctions3.3. MOS Transistors3.4. Advanced MOS Modeling3.5. Bipolar-Junction Transistors3.6. SPICE-Modeling Parameters3.7. Appendix3.8. SPICE Simulations3.9. Bibliography3.10. Problems3.11. Device Model Summary4. TRADITIONAL MOS DESIGN4.1. Pseudo-NMOS Logic4.2. Pseudo-NMOS Logic Gates4.3. Transistor Equivalency4.4. CMOS Logic4.5. CMOS Gate Design4.6. SPICE Simulations4.7. Bibliography4.8. Problems5. TRANSMISSION-GATE AND FULLY DIFFERENTIAL CMOS LOGIC5.1. Transmission-Gate Logic Design5.2. Differential CMOS Circuits5.3. Bibliography5.4. Problems6. CMOS TIMING AND I/O CONSIDERATIONS6.1. Delay of MOS Circuits6.2. Input/Output Circuits6.3. Bibliography6.4. Problems7. LATCHES, FLIP-FLOPS, AND SYNCHRONOUS SYSTEM DESIGN7.1. CMOS Clocked Latches7.2. Flip-flops7.3. CMOS Flip-flops7.4. Synchronous System Design Techniques7.5. Synchronous System Examples7.6. Bibliography7.7. Problems8. BIPOLAR AND BiCMOS LOGIC GATES8.1. Emitter-Coupled Logic Gates8.2. Current-Mode Logic8.3. BiCMOS8.4. SPICE Simulations8.5. Bibliography8.6. Problems9. ADVANCED CMOS LOGIC DESIGN9.1. Pseudo-NMOS and Dynamic Precharging9.2. Domino-CMOS Logic9.3. No-Race-Logic9.4. Single-Phase Dynamic Logic9.5. Differential CMOS9.6. Dynamic Differential Logic9.7. Bibliography9.8. Problems10. DIGITAL INTEGRATED SYSTEM BUILDING BLOCKS10.1. Multiplexors and Decoders10.2. Barrel Shifters10.3. Counters10.4. Digital Adders10.5. Digital Multipliers10.6. Programmable Logic Arrays10.7. Bibliography10.8. Problems11. INTEGRATED MEMORIES11.1. Static Random-Access Memories11.2. Static Random-Access Memory Storage Cells11.3. Address Buffers and Decoders11.4. Dynamic Bus Precharge and Address-Transition-Detect Circuits11.5. Modifications for Large Static Random-Access Memories11.6. Dynamic Random-Access Memories11.7. Read-Only Memories11.8. Bibliography11.9. Problems12. GaAs DIGITAL CIRCUITS12.1. Introduction12.2. GaAs Processing and Components12.3. MESFET Modeling12.4. MESFET Second-Order Effects12.5. Logic Design with MESFETs12.6. Capacitively Enhanced Logic12.7. GaAs Logic Family Comparison12.8. Heterojunction Bipolar Technology12.9. Bibliography12.10. Problems13. DIGITAL SYSTEM TESTING13.1. Conservative Design Principles13.2. Scan-Design Techniques13.3. Localized Test-Vector Generation and Test-Output Compression Techniques13.4. Boundary-Scan Testing13.5. Bibliography13.6. ProblemsIndex