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Overview
Product Details
| ISBN-13: | 9780792391265 |
|---|---|
| Publisher: | Springer-Verlag New York, LLC |
| Publication date: | 01/01/1991 |
| Pages: | 240 |
| Product dimensions: | 6.14(w) x 9.21(h) x 0.56(d) |
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Chapter 6: Logic Synthesis
Our view of the language so far has been toward modeling and simulating logic hardware. We have presented language constructs that can be used to specify the intricate functionality and timing of a circuit. Using this approach, we can simulate a design using timing parameters based on circuits that have been placed and routed, giving great confidence in the results of the simulation. In this chapter, we consider an alternate view of the language: synthesis. When using the language as an input specification for synthesis, the concern is specifying a functionally correct system while allowing a synthesis CAD tool to design the final gate level structure of the system. These views of the language are complementary. However, care must be taken in writing a description that will be used in both simulation and synthesis.6.1 Overview of Synthesis
The predominate synthesis technology in use today is logic synthesis. A system is specified at the register-transfer level of design, and, by using logic synthesis tools, a gate level implementation of the system can be obtained. The synthesis tools are capable of optimizing a design with respect to various constraints, including timing and/or area. They use a technology library file to specify the components to be used in the design. Writing Verilog specifications for logic synthesis tools will be discussed in this chapter.
6.1.1 Register-Transfer Level Systems
A register- transfer level description may contain different features; parts of the description may be purely combinational while others may specify sequential elements such as latches and flip flops. There may also be a finite state machine description, specifying a state transition graph.
A logic synthesis tool compiles a register-transfer level design using two main phases. The first is a technology independent phase where the design is read in and manipulated without regard to the final implementation technology. In this phase, major simplifications in the combinational logic may be made. The second phase is technology mapping where the design is transformed to match the components in a component library. If there are only two-input gates in the library, the design is transformed so that each logic function is implementable by a component in the library. Indeed, synthesis tools can transform one gate level description into another, providing the capability of redesigning a circuit when a new technology library is used.
The attraction of a logic synthesis CAD tool is that it aids in a fairly complex design process. (After all, did your logic design professor ever tell you what to do when the Karnaugh map had more than five or six variables!) These tools target large combinational design and different technology libraries, providing implementation trade-offs in time and area. Further, they promise functional equivalence of the initial specification and its resulting implementation. Given the complexity of this level of design, these tools improve the productivity of designers in many common design situations.
To obtain this increased productivity, we must specify our design in a way that it can be simulated for functional correctness and then synthesized. Whereas the earlier parts of this book focussed on the semantics of the full language and how it can be used to model intricate timing and behavior, this chapter discusses methods of describing register-transfer level systems for input to logic synthesis tools.
6.1.2 Disclaimer
The first part of this chapter defines what a synthesizable description for logic synthesis is. There are behaviors that we can describe but that common logic synthesis tools will not be able to design. (Or they may design something you'd want your competitor to implement!) Since synthesis technology is still young, and the task of mapping an arbitrary behavior on to a set of library components is complex, arbitrary behavior specifications are not allowed as inputs to logic synthesis tools. Thus, only a subset of the language may be used for logic synthesis, and the style of writing a description using that subset is restricted. The first part of this chapter describes the subset and restrictions commonly found in logic synthesis specification today. As logic synthesis technology matures, the set of allowable constructs will probably expand and the style restrictions will probably lessen; -hey both have evolved over the last several years....
Table of Contents
- Preface
- Acknowledgments
- Ch. 1 Verilog - A Tutorial Introduction
- Ch. 2 Behavioral Modeling
- Ch. 3 Concurrent Processes
- Ch. 4 Logic Level Modeling
- Ch. 5 Advanced Timing
- Ch. 6 Logic Synthesis
- Ch. 7 Behavioral Synthesis
- Ch. 8 User-Defined Primitives
- Ch. 9 Switch Level Modeling
- Ch. 10 Projects
- App. A Tutorial Questions and Discussion
- App. B Lexical Conventions
- App. C Verilog Operators
- App. D Verilog Gate Types
- App. E Registers, Memories, Integers, and Time
- App. F System Tasks and Functions
- App. G Formal Syntax Definition
- Acknowledgments