Testing and Reliable Design of CMOS Circuits / Edition 1

by Niraj K. Jha, Sandip Kundu

Overview

In the last few years CMOS technology has become increasingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den­ sity and low power requirement. The ability to realize very com­ plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance­ ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the importance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

Product Details

ISBN-13:	9780792390565
Publisher:	Springer US
Publication date:	12/31/1989
Series:	The Springer International Series in Engineering and Computer Science , #88
Edition description:	1990
Pages:	232
Product dimensions:	6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

1. Introduction.- 1.1 What is Testing—.- 1.2 Faults and Errors.- 1.3 Different Types of CMOS Circuits.- 1.4 Gate-Level Model.- 1.5 Fault Models.- References.- Problems.- 2. Test Invalidation.- 2.1 The Test Invalidation Problem.- 2.2 Robust Testability of Dynamic CMOS Circuits.- References.- Additional Reading.- Problems.- 3. Test Generation for Dynamic CMOS Circuits.- 3.1 Path Sensitization and D-Algorithm.- 3.2 Boolean Difference.- 3.3 Fault Collapsing.- 3.4 Redundancy in Circuits.- 3.5 Testing of Domino CMOS Circuits.- 3.6 Testing of CVS Circuits.- References.- Additional Reading.- Problems.- 4. Test Generation for Static CMOS Circuits.- 4.1 Non-Robust Test Generation.- 4.2 Robust Test Generation.- References.- Additional Reading.- Problems.- 5. Design for Robust Testability.- 5.1 Testable Designs Using Extra Inputs.- 5.2 Testable Designs Using Complex Gates.- 5.3 Testable Designs Using Parity Gates.- 5.4 Testable Designs Using Shannon’s Theorem.- References.- Additional Reading.- Problems.- 6. Self-Checking Circuits.- 6.1 Concepts and Definitions.- 6.2 Error-Detecting Codes.- 6.3 Self-Checking Checkers.- 6.4 Self-Checking Functional Circuits.- References.- Additional Reading.- Problems.- 7. Conclusions.- References.