Nano-CMOS Circuit and Physical Design / Edition 1

by Ban Wong, Anurag Mittal, Yu Cao, Greg W. Starr

Overview

Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.

Product Details

ISBN-13:	9780471466109
Publisher:	Wiley
Publication date:	11/29/2004
Series:	IEEE Press
Pages:	393
Product dimensions:	6.25(w) x 9.50(h) x 0.95(d)

About the Author

BAN P. WONG, IENG MIEE, served for five years as a member of the technical program committee of IEEE International Solid-State Circuits Conference and as session chair, cochair, and organizer of a panel session. He has three issued patents. He has led circuit design teams in developing methodology and implementation of high-performance and low-power microprocessors. He is currently Senior Engineering Manager for NVIDIA Corporation.

ANURAG MITTAL received his PhD in applied physics from Yale University. He has codeveloped novel embedded NVM microcontroller and microprocessor solutions including the world’s first truly CMOS-compatible Flash technology. He is Senior Staff Engineer for Virage Logic, Inc.

YU CAO received his PhD in electrical engineering from University of California, Berkeley. He is a postdoctoral researcher in the Berkeley Wireless Research Center. He received the 2000 Beatrice Winner Award at the IEEE International Solid-State Circuits Conference.

GREG STARR received his PhD in electrical engineering from Arizona State University. Currently, he is a Senior Design Manager at Xilinx Corporation.

Read an Excerpt

Nano-CMOS Circuit and Physical Design

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By Ban P. Wong Anurag Mittal Yu Cao Greg Starr

John Wiley & Sons

Copyright © 2005 John Wiley & Sons, Inc.
All right reserved.
ISBN: 0-471-46610-7

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Chapter One

NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS

1.1 DESIGN METHODOLOGY IN THE NANO-CMOS ERA

As process technology scales beyond 100-nm feature sizes, for functional and high-yielding silicon the traditional design approach needs to be modified to cope with the increased process variation, interconnect processing difficulties, and other newly exacerbated physical effects. The scaling of gate oxide (Figure 1.1) in the nano-CMOS regime results in a significant increase in gate direct tunneling current. Subthreshold leakage and gate direct tunneling current (Figure 1.2) are no longer second-order effects. The effect of gate-induced drain leakage (GIDL) will be felt in designs, such as DRAM (Chapter 7) and low-power SRAM (Chapter 9), where the gate voltage is driven negative with respect to the source. If these effects are not taken care of, the result will be a nonfunctional SRAM, DRAM, or any other circuit that uses this technique to reduce subthreshold leakage. In some cases even wide muxes and flip-flops may be affected.

Subthreshold leakage and gate current are not the only issues that we have to deal with at a functional level, but also the power management of chips for high-performance circuits such asmicroprocessors, digital signal processors, and graphics processing units. Power management is also a challenge in mobile applications.

Furthermore, optical lithography will be stretched to the limit even when enhanced resolution extension technologies (RETs) are employed. These techniques result in increased cost of the mask and longer fabrication turnaround time. It is no longer cost-effective to respin the design several times to get to a production-worthy design. In the past, processor designers would tape out their design when the verification confidence level was around 98%. Debug continued on silicon, which is usually several orders of magnitude faster and would result in getting a product to market sooner. Now, due to the increased mask cost and longer fabrication turnaround time, the trade-off to arrive at the most cost-effective product and shortest time to market will certainly be different.

Since design rules do not all shrink at the same rate, legacy designs must be reworked completely for the next node unless one anticipates the shifting rules and sacrifices density at previous nodes so that the design is scalable without redesign of the physical layout. There is still a need to resimulate the critical circuits, and that, too, can be minimized if one uses scaling-friendly circuit techniques. This will require prior thought and design rule trade-offs to achieve a scalable design, so that a faster and smaller chip for a cost-effective midlife performance boost can be realized through process scaling with a minimum, if any, rework. The key in foreseeing the changing trend in design rules is a good understanding of the process difficulties and tooling limitations, which are covered in detail in subsequent chapters.

1.2 INNOVATIONS NEEDED TO CONTINUE PERFORMANCE SCALING

The transistor figure of merit (FOM) is now deviating from the reciprocal of the gate length. As can be seen in Figure 1.3, the fanout-of-4 delay is tailing off with advancing technology. Furthermore, global wiring is not scaling, whereas wire resistance below 0.1 µm is increasing exponentially. This is due primarily to surface scattering and grain-size limitations in a narrow trench, resulting in carrier scattering and mobility degradation. The gate dielectric thickness is approaching atomic dimensions and at 1.2 nm in the 90-nm node is about five atomic layers of oxide. Figure 1.1 shows that gate oxide scaling is slowing as it approaches the limit, which is one atomic layer thick. Source-drain extension resistance (RSD) is getting to be a larger proportion of the transistor "on" resistance. Source-drain extension doping has been increased significantly for the 130-nm node, and the ability to reduce this resistance has to be traded off with other short-channel effects, such as hot-carrier injections (HCIs) and leakage current due to band-to-band tunneling. Source-drain diffusions are getting so thin that implants are at the saturation level and resistance can no longer be reduced unless additional dopants can be activated.

Poly lines are getting to be quite narrow, between 70 and 90 nm for the 130-nm node and 50 nm for the 90-nm node (see Figure 1.4). This requires a trade-off between poly sheet resistance and source-drain leakage. To lower the narrow poly line resistance would require more silicidation of the poly. Since the silicidation process is common between poly and source-drain diffusion, increasing silicidation of the poly would result in higher silicide consumption of source and drain diffusions. Due to the extreme shallow junctions at the source and drain, this can result in punch-through as a result of silicide consumption of the source-drain diffusion. Research is ongoing to bring raised source-drain technology online to mitigate this effect for the 65-nm node and possibly for the 90-nm node as well. Some manufacturers might be able to bring this technique online by the later part of the 90-nm node.

Starting at the 180-nm technology node, the critical feature size (poly) is already subwavelength compared to the ultraviolet (UV) wavelength used in lithography. The gap is increasing at each subsequent technology node (see Figure 1.5). At the 65-nm technology node, even with aggressive RET, 193-nm lithography will run out of gas. To extend the resolution of 193-nm scanners, research is ongoing to increase the numerical aperture (NA) of the lithography system, including immersion lithography. More details on the challenges of lithography are presented in Chapter 3. The challenges of 157-nm and extreme UV (EUV) lithography are monumental and will increase tooling and mask costs and fabrication turnaround time. If 157-nm lithography is not brought online by the 65-nm technology node, we will see the subwavelength gap widen further. Circuit and physical designers can no longer design simply by technology design rules and expect a functional, let alone a scalable design that also meets varied design goals, such as high performance and low-power mobile applications from a single mask set. Designers must know when to use more relaxed rules and not simply relax the rules on the entire design, which negates physical scaling.

Combinations of materials and processes used to fabricate new structures create integration complexities that require design and layout solutions. Process engineers and technology developers will not be able to resolve all the issues that arise as a result of sub-100-nm scaling, which includes integration complexities and fabrication and process control difficulties. We will suggest techniques that circuit and physical designers can employ to mitigate the challenges of working with sub-100-nm technologies, and provide some understanding of the process technology with which they are designing. Similarly, it is important for process engineers to understand the basis of physical design so that the technology can be tailored for a robust and scalable design that can continue with both physical and performance scaling.

It will require some innovation on the part of technology developers to bring new processes online, and will necessitate the development of new materials as well. It is an undisputed fact that performance scaling derived from mere physical scaling has already reached an inflection point and is no longer providing much, if any, gain in performance. To continue performance scaling we have already witnessed some innovations at work and more are under development. Silicon-on-insulator (SOI) technology has been shown to improve transistor performance by about 20 to 30%, depending on the source of the data. Some microprocessors have already adopted SOI as the technology of choice. Strained silicon using relaxed silicon-germanium substrates has been demonstrated to offer up to 30% improvement in carrier mobility. Since these substrates are expensive and are prone to dislocation defects, they are not as widely accepted.

An innovation that demonstrates yet another method of achieving strain in silicon for carrier mobility improvement is use of a nitride capping layer. Such a layer generates strain due to the compressive stresses on source-drain diffusion, thus creating strain in the transistor channel as the source-drain diffusions are pulled apart. This works only at 90-nm node and below because of the need for the channel to be in close proximity to source-drain stress. A longer-channel device will see less gain. Even at the 90-nm nodes transistors with drawn length longer than minimum will have diminished gain. Unfortunately, at the 130-nm node, this option for performance improvement is limited. This technique will be the preferred method to create strain since it requires no special substrates, and no dislocation has been seen so far. Best of all, it requires no extra steps, just a recipe change.

The switch to copper interconnects gave short-term relief on pressure to continue performance scaling in the near-limit regime. This is an example of an innovation that required a material change. Many other out-of-the-box innovations are in the pipeline, including raised source-drain (SD) diffusion, dual-gate FET, FinFET, high-[kappa] gate dielectrics, and metal gates. Whether they will pan out depends on the risks versus the benefits, as well as the cost, integration and fabrication complexity and turnaround time.

1.3 OVERVIEW OF SUB-100-NM SCALING CHALLENGES AND SUBWAVELENGTH OPTICAL LITHOGRAPHY

1.3.1 Back-End-of-Line Challenges (Metallization)

Metal Resistance Line width below 0.1 µm is accompanied by an exponential increase in resistivity. The higher-resistivity barrier material is becoming a larger proportion of the conductor cross-sectional area for narrower lines. Reduced electron mobility due to surface scattering plays a part in the increased resistivity. Narrow lines result in smaller grains, which cannot be recrystallized into larger grains while encased in a narrow groove thus increasing the resistivity further.

Furthermore, variations in critical dimensions (CDs) of the barrier material and groove (line width) result in larger resistance variation. These, along with chemical-mechanical planarization (CMP) dishing and erosion, as well as lithographic and etch distortions, cause further variation in the line resistance (Figure 1.6).

Interconnect RC values are increasing at the 130-nm node and getting worse for both local and global wiring beyond the 130-nm node. As explained above, resistivity is increasing (see Figure 2.25) while the scaled capacitance is not decreasing, leading to increased delay for local wiring even though the length of local wires is getting shorter (Figures 1.7 to 1.9). The length of global wires is not reduced since chip size is not being reduced as more functionality is added to new designs. For example, the Pentium 4 Willamette core in the 180-nm process had 42 million transistors; for the Northwood core in the 130-nm process, the number of transistors increased to 55 million. This is because the L2 cache increased from 256 kB to 512 kB for the Northwood core. The fraction of reachable area in a clock cycle is diminishing as the technology scales. This is further exacerbated for designs in the advanced technology nodes by the increase in clock frequency while the die size is not decreasing.

Interconnect Dielectric Constant Low-[kappa] dielectric enables wire scaling in the nano-CMOS regime but is getting harder to implement as width and space are decreasing. Low-[kappa] dielectric also poses potential leakage and reliability hazards, due to time-dependent dielectric breakdown (TDDB) in narrowly spaced lines. Packaging difficulties dictate the need to form a "hard crust" to provide a mechanically sound die against the stresses imposed on a chip by the packaging processes. This crust means that higher-dielectric-constant material is needed for the upper layers of the metal stack, somewhat reducing the effectiveness of the low-[kappa] metal technology. Low-[kappa] dielectric will be limited to four or five layers of metallization in eight- or nine-layer metal technology. The mitigating factors are the way the upper metals are used. Normally, the upper layer metals are used for power distribution. In most designs they are also used as clock distribution layers, thus increasing the power of the clock network and also requiring more stages to buffer up from the PLL, resulting in higher skew as well.

Low-[kappa] Interconnect Roll-out Lagging Significantly The lag in the introduction of low-[kappa] technology is due to problems with copper barrier material, mechanical integrity against bumping force during packaging, and a host of fabrication process issues. This has resulted in several manufacturers reverting to fluoro-silicate glass (FSG) dielectric.

Low-[kappa] dielectric is like jelly and very porous, and thus it is susceptible to moisture and contaminant absorption and outgassing. Since the material is soft, it suffers from CMP ripouts, causing yield loss and erosion, affecting wire resistivity as well. Low-[kappa] dielectric is also a poor conductor of heat, thus degrading the electromigration (EM) property of the interconnect, negating to some extent the good EM property of copper.

Interconnect Figure of Merit The unscaled interconnect FOM has been decreasing at every technology node (see Figures 1.7 to 1.9). In the past, transistor performance was lagging. We have arrived at a point where the interconnect performance will be the chip performance limiter. Local interconnect performance will not scale, while global wiring is getting really slow, especially if wire length does not scale due to additional functions. Chip size invariably stays at the same size as in previous designs, despite technology scaling, due to increased functionality of newer designs. In other cases, as in microprocessors, chip size actually increases despite technology scaling. As the chip grows larger despite scaling, we need global wires to ship signals between blocks.

It has been predicted that the fraction of the total chip area reachable in one cycle will diminish as we scale the technology, while the clock frequency increases. This will force designers to insert more repeaters on global wires, and in some cases pipelining of the global signals may be necessary, so that interconnect-dominated paths can scale better and will not be frequency-limiting paths. However, this will increase chip area, power consumption, and clock load, as well as increasing the complexity for full-chip timing. The result of higher clock load translates into higher clock skew as well.

Continues...

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Excerpted from Nano-CMOS Circuit and Physical Design by Ban P. Wong Anurag Mittal Yu Cao Greg Starr Copyright © 2005 by John Wiley & Sons, Inc.. Excerpted by permission.
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Table of Contents

FOREWORD.

PREFACE.

1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS.

1.1 Design Methodology in the Nano-CMOS Era.

1.2 Innovations Needed to Continue Performance Scaling.

1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography.

1.4 Process Control and Reliability.

1.5 Lithographic Issues and Mask Data Explosion.

1.6 New Breed of Circuit and Physical Design Engineers.

1.7 Modeling Challenges.

1.8 Need for Design Methodology Changes.

1.9 Summary.

References.

PART I: PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS.

2 CMOS DEVICE AND PROCESS TECHNOLOGY.

2.1 Equipment Requirements for Front-End Processing.

2.2 Front-End-Device Problems in CMOS Scaling.

2.3 Back-End-of-Line Technology.

References.

3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY.

3.1 Introduction and Simple Imaging Theory.

3.2 Challenges for the 100-nm Node.

3.3 Resolution Enhancement Techniques: Physics.

3.4 Physical Design Style Impact on RET and OPC Complexity.

3.5 The Road Ahead: Future Lithographic Technologies.

References.

PART II: PROCESS SCALING IMPACT ON DESIGN 4 MIXED-SIGNAL CIRCUIT DESIGN.

4.1 Introduction.

4.2 Design Considerations.

4.3 Device Modeling.

4.4 Passive Components.

4.5 Design Methodology.

4.6 Low-Voltage Techniques.

4.7 Design Procedures.

4.8 Electrostatic Discharge Protection.

4.9 Noise Isolation.

4.10 Decoupling.

4.11 Power Busing.

4.12 Integration Problems.

4.13 Summary.

References.

5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN.

5.1 Introduction.

5.2 ESD Standards and Models.

5.3 ESD Protection Design.

5.4 Low-C ESD Protection Design for High-Speed I/O.

5.5 ESD Protection Design for Mixed-Voltage I/O.

5.6 SCR Devices for ESD Protection.

5.7 Summary.

References.

6 INPUT/OUTPUT DESIGN.

6.1 Introduction.

6.2 I/O Standards.

6.3 Signal Transfer.

6.4 ESD Protection.

6.5 I/O Switching Noise.

6.6 Termination.

6.7 Impedance Matching.

6.8 Preemphasis.

6.9 Equalization.

6.10 Conclusion.

References.

7 DRAM.

7.1 Introduction.

7.2 DRAM Basics.

7.3 Scaling the Capacitor.

7.4 Scaling the Array Transistor.

7.5 Scaling the Sense Amplifier.

7.6 Summary.

References.

8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS.

8.1 Introduction.

8.2 Interconnect Parasitics Extraction.

8.3 Signal Integrity Analysis.

8.4 Design Solutions for Signal Integrity.

8.5 Summary.

References.

9 ULTRALOW POWER CIRCUIT DESIGN.

9.1 Introduction.

9.2 Design-Time Low-Power Techniques.

9.3 Run-Time Low-Power Techniques.

9.4 Technology Innovations for Low-Power Design.

9.5 Perspectives for Future Ultralow-Power Design.

References.

PART III: IMPACT OF PHYSICAL DESIGN ON MANUFACTURING/YIELD AND PERFORMANCE.

10 DESIGN FOR MANUFACTURABILITY.

10.1 Introduction.

10.2 Comparison of Optimal and Suboptimal Layouts.

10.3 Global Route DFM.

10.4 Analog DFM.

10.5 Some Rules of Thumb.

10.6 Summary.

References.

11 DESIGN FOR VARIABILITY.

11.1 Impact of Variations on Future Design.

11.2 Strategies to Mitigate Impact Due to Variations.

11.3 Corner Modeling Methodology for Nano-CMOS Processes.

11.4 New Features of the BSIM4 Model.

11.5 Summary.

References.

INDEX.