Interaction Between Compilers and Computer Architectures / Edition 1

by Gyungho Lee, Pen-Chung Yew

Overview

Effective compilers allow for a more efficient execution of application programs for a given computer architecture, while well-conceived architectural features can support more effective compiler optimization techniques. A well thought-out strategy of trade-offs between compilers and computer architectures is the key to the successful designing of highly efficient and effective computer systems. From embedded micro-controllers to large-scale multiprocessor systems, it is important to understand the interaction between compilers and computer architectures.
The goal of the Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT) is to promote new ideas and to present recent developments in compiler techniques and computer architectures that enhance each other's capabilities and performance. Interaction Between Compilers and Computer Architectures is an updated and revised volume consisting of seven papers originally presented at the Fifth Workshop on Interaction between Compilers and Computer Architectures (INTERACT-5), which was held in conjunction with the IEEE HPCA-7 in Monterrey, Mexico in 2001. This volume explores recent developments and ideas for better integration of the interaction between compilers and computer architectures in designing modern processors and computer systems.
Interaction Between Compilers and Computer Architectures is suitable as a secondary text for a graduate level course, and as a reference for researchers and practitioners in industry.

Product Details

ISBN-13:	9781441948960
Publisher:	Springer US
Publication date:	12/06/2010
Series:	The Springer International Series in Engineering and Computer Science , #613
Edition description:	Softcover reprint of hardcover 1st ed. 2001
Pages:	143
Product dimensions:	6.10(w) x 9.25(h) x 0.01(d)

Table of Contents

1 EquiMax Optimal Scheduling Formulation.- 2 An Efficient Semi-Hierarchical Array Layout.- 3 Impact of Tile-Size Selection for Skewed Tiling.- 4 Improving Software Pipelining by Hiding Memory Latency.- 5 Register Allocation for Embedded System.- 6 Is Compiling for Performance == Compiling for Power?.- 7 A Technology-Scalable Architecture for Fast Clocks and High ILP.- Topic Index.- Author Index.