This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.
• Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
• Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
• Enables designers to build hardware implementations that are resilient to a variety of side-channels.
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• Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
• Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
• Enables designers to build hardware implementations that are resilient to a variety of side-channels.
Hardware Architectures for Post-Quantum Digital Signature Schemes
This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.
• Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
• Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
• Enables designers to build hardware implementations that are resilient to a variety of side-channels.
• Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
• Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
• Enables designers to build hardware implementations that are resilient to a variety of side-channels.
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Hardware Architectures for Post-Quantum Digital Signature Schemes
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Hardware Architectures for Post-Quantum Digital Signature Schemes
170Paperback(1st ed. 2021)
$119.99
119.99
In Stock
Product Details
ISBN-13: | 9783030576844 |
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Publisher: | Springer International Publishing |
Publication date: | 10/28/2020 |
Edition description: | 1st ed. 2021 |
Pages: | 170 |
Product dimensions: | 6.10(w) x 9.25(h) x (d) |
About the Author
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