eBook
Available on Compatible NOOK devices, the free NOOK App and in My Digital Library.
Related collections and offers
Overview
New features in the 2nd edition:
- Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs.
- Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS.
- Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications
- Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-digitation, and common centroid techniques.
- Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5.
- Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges.
ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit&semiconductor engineers and quality, reliability &analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.
Product Details
| ISBN-13: | 9781118954485 |
|---|---|
| Publisher: | Wiley |
| Publication date: | 04/24/2015 |
| Sold by: | JOHN WILEY & SONS |
| Format: | eBook |
| Pages: | 560 |
| File size: | 30 MB |
| Note: | This product may take a few minutes to download. |
About the Author
Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” Voldman was a member of the semiconductor development of IBM, Qimonda, and Intersil and worked as a full time consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) and a consultant on latchup, for the Samsung Electronics Corporation. He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally reaching over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, China and Senegal. He is a recipient of 252 issued US patents and has written over 150 technical papers. He has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents.
Dr. Voldman is an author of the book series including ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design,, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of booksare also released.
Read an Excerpt
ESD
Circuits and DevicesBy Steven Howard Voldman
John Wiley & Sons
Copyright © 2006 John Wiley & Sons. Ltd.All right reserved.
ISBN: 0-470-84754-9
Chapter One
Electrostatic Discharge1.1 ELECTRICITY AND ELECTROSTATICS DISCHARGE
1.1.1 Electricity and Electrostatics
In the field of electricity, electrostatics, and circuit theory, there are many discoveries and accomplishments that have lead to the foundation of the field of electrostatic discharge (ESD) phenomenon. Below is a chronological list of key events that moved the field of electrostatics forward:
600 B.C. Thales of Miletus discovers electrostatic attraction.
1600 A.D. William Gilbert proposes the "electric fluid" model.
1620 A.D. Niccolo Cabeo discusses "attractive" and "repulsive" phenomena.
1729 A.D. Stephen Gray demonstrates "electricity" can be transferred by wires.
1733 A.D. Charles Francois du Fay discusses two kinds of electricity-"resinous" and "vitreous."
1749 A.D. Abbey Jean-Antoine Nollet invents the two-fluid model of electricity.
1745 A.D. Pieter Van Musschenbroeck invents the Leyden jar, or the capacitor.
1747 A.D. Benjamin Franklin proposes single fluid model, with "positive" and "negative" charge.
1748 A.D. Sir William Watson develops the first "glow discharge."
1759 A.D. Francis Ulrich Theodore Aepinus discusses "charging by induction."
1766 A.D. Joseph Priestley deduces the electric force follows an inverse square law.
1775 A.D. Henry Cavendish invents the concept of capacitance and resistance.
1785 A.D. Charles Augustin Coulomb verifies the inverse square law relationship.
1812 A.D. Simeon Denis Poisson demonstrates that charge resides on the surface of a conductor.
1821 A.D. Humphrey Davy establishes the geometrical and thermal effects of resistance.
1826 A.D. Ohm develops the relationship between potential, resistance, and current.
1837 A.D. Michael Faraday discovers the concept of dielectric constants in materials.
1841 A.D. James Prescott Joule shows relationship of electrical current and thermal heating.
1848 A.D. Gustav Kirchoff extends the concept of Ohm's law.
1873 A.D. James Clerk Maxwell publishes the work Treatise of Electricity and Magnetism.
1889 A.D. Paschen establishes a relationship explaining the electrical breakdown of gases.
1906 A.D. Toepler establishes a relationship for arc resistance in a discharge process.
1915 A.D. Townsend explains avalanche phenomena in materials.
1.1.2 Electrostatic Discharge
In the field of ESD, accomplishments to advance the field of electrostatic discharge phenomena are in the form of development of experimental discovery, analytical models, introduction of new semiconductor devices and circuits, test equipment, as well as the development of ESD standards. Below is a short chronological list of key events that moved the field of ESD:
1968 A.D. D. Wunsch and R. R. Bell introduces the power-to-failure electro-thermal model in the thermal diffusion time constant regime.
1970 A.D. D. Tasca develops the power-to-failure electro-thermal model in the adiabatic and steady-state time constant regime.
1971 A.D. Vlasov and Sinkevitch develops a physical model for electro-thermal failure of semiconductor devices.
1972 A.D. W. D. Brown evaluates semiconductor devices under high-amplitude current conditions.
1981 A.D. J. Smith and W. R. Littau develops an electro-thermal model for resistors in the thermal diffusion time regime.
1981 A.D. Enlow, Alexander, Pierce, and Mason addresses the statistical variation of the power-to-failure of bipolar transistors due to semiconductor manufacturing process, and ESD event variations.
1983 A.D. M. Ash evaluates the non-linear nature of the power threshold and the temperature dependence of the physical parameters establishing the Ash relationship.
1983 A.D. V. I. Arkihpov, E. R. Astvatsaturyan, V. I. Godovosyn, and A. I. Rudenko derives the cylindrical nature of the electro-current constriction.
1985 A.D. T. J. Maloney and N. Khurana discusses transmission line pulse (TLP) testing as a method for semiconductor I-V characterization and modeling.
1989 A.D. Dwyer, Franklin, and Campbell extends the Wunsch-Bell model to address three-dimensional effects.
1989 A.D. R. Renninger, M. Jon, D. Lin, T. Diep, and T. Welser introduces the first field-induced charged device model (CDM) device simulator.
1989 A.D. T. Polgreen and P. Chatterjee explain non-uniform current flow in silicided multi-finger MOSFETs.
1992 A.D. M. Hargrove and S. Voldman quantify CMOS ESD networks in the first CMOS shallow trench isolation (STI) technology.
1992 A.D. S. Voldman discovers the effect of MeV implanted retrograde well dose on ESD robustness.
1993 A.D. D. Lin publishes the first paper on the effect of MOSFET dielectric and junction breakdown scaling on on-chip ESD protection.
1993 A.D. S. Voldman publishes the first paper on the influence on MOSFET constant electric field scaling theory on ESD robustness [16]. A "Constant ESD scaling" theory is developed under the constraint of maintaining ESD robustness as technology is scaled.
1993 A.D. ESD Association releases the human body model (HBM) standard for semiconductor component testing.
1993 A.D. H. Geiser introduces the very fast transmission line pulse (VF-TLP) ESD test system.
1994 A.D. A. Ameresekera and C. Duvvury publishes on the influence of MOSFET scaling trends on ESD robustness.
1994 A.D. ESD Association releases the machine model (MM) standard for semiconductor component testing.
1995 A.D. A. Wallash releases the first publication on ESD failure mechanisms in magneto-resistor (MR) recording heads. The significance of the work was the first indication of ESD concerns in the magnetic recording and disk drive industry.
1995 A.D. SEMATECH initiates ESD Working Group to address ESD strategic planning. The SEMATECH effort addresses ESD technology benchmarking, ESD technology roadmap and test equipment, ESDA and JEDEC ESD specification alignment, and TLP test standard development.
1996 A.D. K. Banerjee develops Ti/Al/Ti interconnect model, extending the work of D. Tasca to modern CMOS interconnects.
1997 A.D. S. Voldman publishes first experimental measurements of ESD in copper (Cu) interconnects, and the comparison to aluminum (Al) interconnects. This work addresses the influence of CMOS interconnect scaling on ESD robustness, and the evolutionary changes from aluminum to copper interconnects.
1997 A.D. ESD Association Device Testing Standards Committee releases first charged device model (CDM) Standard.
1997 A.D. J. Barth introduces the first commercial transmission line pulse (TLP) device simulator. The introduction of commercial systems has lead to the acceptance of the TLP methodology for ESD sensitivity testing of semiconductors.
1998 A.D. SEMATECH Quality and Reliability ESD Working Group initiates transmission line pulse (TLP) standards effort.
2000 A.D. S. Voldman and P. Juliano published the first ESD measurements in Silicon Germanium (SiGe) technology. The significance of this work is the beginning of the focus of ESD in radio frequency (RF) technology.
2002 A.D. R. Gibson and J. Kinnear initiate the S20.20 ESD Control Certification Program. The significance of this effort is the focus on international certification of ESD control programs.
2003 A.D. Oryx Instruments and Thermo KeyTek, introduces commercial very fast transmission line pulse (VF-TLP) systems. The significance of this work is the introduction of VF-TLP systems as a standard testing methodology for future ESD testing.
2004 A.D. ESD Association Device Testing Standards Committee initiates the transmission line pulse (TLP) Standard Practice document. The significance of this work is the acceptance of TLP as a standard testing methodology in the semiconductor industry.
1.1.3 Key ESD Patents, Inventions, and Innovations
In the field of ESD protection, there are many patents, inventions, and innovations that stimulated growth of ESD circuits as well as improved the ESD robustness of circuits themselves. ESD circuit inventions are important in providing innovations and techniques that improve the ESD robustness of semiconductor chips. Interest in ESD patenting of ESD protection networks began in the 1970s, with a continued growth in patent activity, invention, and innovations. Below is a chronological list of key innovations that moved the field of ESD protection forward in the area of ESD circuits. In some cases, no patent for the invention was pursued. Many of the patents chosen in this listing consist of the ESD design practices and subjects and topics which will be discussed in the text. Starting from the 1970s, here is a listing of key circuit innovations and those which will be referred to in the future chapters:
1970 A.D. M. Fischer (IBM). Resistor-thick oxide FET gate protection device for thin oxide FETs. IBM Technology Disclosure Bulletin 13 (5): 1272-1273. This introduced the use of a gate-coupled "thick oxide" field effect transistor and a series resistor element. This invention discloses the concept of using a thick oxide insulated gate field effect transistor (IGFET) to protect a thin oxide IGFET.
1971 A.D. Boss et al. (IBM). ESD network with capacitor divider and half-pass transmission gate. IBM Technology Disclosure Bulletin. This introduced the concept of using a capacitive divider across a half-pass transmission gate to reduce the gate oxide stress.
1971 A.D. M. Lenzlinger (RCA). ESD distributed diode/resistor double-diode network. RCA Corporation, CD 4013. Publication: "Gate Protection of MIS Devices", M. Lenzlinger, IEEE Transactions on Electron Device ED-18 (4): 1971. This publication discloses the concept of a double-diode ESD network as well as a distributed diode-resistor transmission line for the diode to [V.sub.DD].
1973 A.D. G. W. Steudel (RCA). Input transient protection for complimentary field effect transistor integrated circuit device. U.S. Patent No. 3,712,995, January 23, 1973. The patent shows a distributed double-diode ESD network with diode/resistor distributed network, but with the reverse polarity.
1974 A.D. T. Enomoto and H. Morita (Mitsubishi). Semiconductor device. U.S. Patent No. 3,819,952, June 25, 1974. The patent shows the use of a first-stage gate-coupled thick oxide insulated gate field effect transistor (IGFET), a series resistor element (prior to the IGFET drain), and a IGFET source resistor element. This first stage is followed by a second-stage thin oxide IGFET whose gate is coupled to the first-stage IGFET source node. The network introduces the concept of a first- and second-stage ESD network, gate-coupling, series resistor options, as well introduces a de-biasing resistor at the source of the first stage.
1979 A.D. C. Bertin (IBM). Over-voltage protective device and circuits for insulated gate transistors. U.S. Patent No. 4,139,935, February 20, 1979. This patent by Claude Bertin was the first process patent that produced a metallurgical junction with a lower breakdown voltage using junction "tailoring" where the breakdown element was to serve as a "gate tie down" or protection network for MOSFET gate oxides.
1983 A.D. N. Sasaki (Fujitsu). Semiconductor integrated circuit device providing a protection circuit. U.S. Patent No. 4,423,431. December 27, 1983. Sasaki introduces the idea of use of a series resistor, and thin oxide transistor as a protection network. The network also introduces gate-coupled thin oxide and a resistor in series with the capacitor. This is the first network that is using gate-coupled thin oxide devices with a resistor on the gate electrode to ground, in a single-stage implementation.
1983 A.D. L. Avery (RCA). Integrated circuit protection device. U.S. Patent No. 4,400,711. August 23, 1983. This patent used a MOSFET in the regenerative feedback loop of a pnpn silicon-controlled rectifier (SCR) for ESD protection applications.
1989 A.D. C. Duvvury and R. Rountree (Texas Instruments). Output buffer with improved ESD protection. U.S. Patent No. 4,855,620, August 8, 1989. This patent is the first patent to discuss the optimization of output buffers for ESD protection improvements.
1990 A.D. R. Rountree (Texas Instruments). Circuit structure with enhanced electrostatic discharge protection. U.S. Patent No. 4,939,616, July 3, 1990. This patent discusses the formation of a low-voltage trigger pnpn silicon-controlled rectifier (SCR) using an n+ diffusion that extends outside of the n-well region to form a lower breakdown voltage and lateral npn element. This innovation was important to produce low-voltage trigger SCRs as technology began to scale.
1992 A.D. A. Graham (Gazelle). Structure for providing electrostatic discharge protection. U.S. Patent No. 5,124,877, June 23, 1992. This patent introduces the concept of a diode string as well as a "ESD discharge reference rail." Today, ESD diode strings are commonly used, as well as the discharge rail concept.
1993 A.D. W. Miller (National Semiconductor). Electrostatic discharge detection and clamp control circuit. U.S. Patent No. 5,255,146, October 19, 1993. This patent was the first patent RC-triggered ESD power clamp network to address the presence of "detection circuits" which respond to the ESD pulse. This is the first patent that addresses the usage of an RC network which is chosen to be responsive to the ESD pulse network.
1993 A.D. R. Merrill (National Semiconductor). Electrostatic discharge protection for integrated circuits. U.S. Patent No. 5,239,440, August 24, 1993. This innovation utilized the RC-discriminator network, inverter logic, and logic circuitry that is parallel to the pre-drive circuitry, and turns on the I/O off-chip driver (OCD) output stage during ESD events.
1993 A.D. Kirsch, G. Gerosa, and S. Voldman (Motorola and IBM). Snubber-clamped ESD diode string network. This network introduced a diode string as a mixed-voltage interface network and solved the reverse-Darlington amplification using a "Snubber" diode element. Implemented into the PowerPC microprocessor and embedded controller family. This was applied to advanced microprocessors for mixed-voltage applications.
1994 A.D. D. Puar (Cirrus Logic). Shunt circuit for electrostatic discharge protection. U.S. Patent No. 5,287,241, February 15, 1994. This introduced the first RC-triggered p-channel MOSFET-based ESD power clamp network.
1994 A.D. J. Pianka (AT&T). ESD protection of output buffers. U.S. Patent No. 5,345,357, September 6, 1994. Development of RC-trigger and gate coupling circuit elements for activation of the output of an n-channel MOSFET pull-up and pull-down off-chip driver (OCD). This ESD technique is especially valuable for small computer system interface (SCSI) chips, since only n-channel output transistors are used as the pull-up and pull-down elements.
1996 A.D. T. J. Maloney (Intel). Electrostatic discharge protection circuits using biased and terminated PNP transistor chains. U.S. Patent No. 5,530,612, June 25, 1996. Maloney's patent application was a second ESD circuit application to address the leakage amplification in diode string ESD networks. This was applied to advanced microprocessors for mixed-voltage applications.
1997 A.D. S. Voldman, S. Geissler, and E. Nowak (IBM). Semiconductor diode with silicide films and trench isolation. U.S. Patent No. 5,629,544, May 13, 1997. This is the first patent that addresses four items: first, it addresses ESD diode structures constructed in shallow trench isolation; second, it addresses STI pull-down effects; it addresses the lateral polysilicon-bound gated ESD p-n diodes; and fourth, the silicon-on-insulator (SOI) lateral ESD gated diode structures.
1997 A.D. D. Krakauer, K. Mistry, S. Butler, and H. Partovi, (Digital Corp). Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps. U.S. Patent No. 5,617,283, April 1, 1997. This was the first ESD application using MOSFETs to establish a MOSFET gate-modulation network. This was applied to microprocessor applications.
(Continues...)
Excerpted from ESD by Steven Howard Voldman Copyright © 2006 by John Wiley & Sons. Ltd.. Excerpted by permission.
All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
Excerpts are provided by Dial-A-Book Inc. solely for the personal use of visitors to this web site.
Table of Contents
About the Author xix
Preface xxi
Acknowledgments xxv
1 Electrostatic Discharge 1
1.1 Electricity and Electrostatic Discharge 1
1.2 Fundamental Concepts of ESD Design 11
1.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 18
1.4 ESD Models 19
1.5 ESD and System-Level Test Models 28
1.6 Time Constants 39
1.7 Capacitance, Resistance, and Inductance and ESD 59
1.8 Rules of Thumb and ESD 62
1.9 ESD Scaling 63
1.10 Lumped versus Distributed Analysis and ESD 65
1.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 79
1.12 ESD Quality and Reliability Business Metrics 84
1.13 Twelve Steps to Building an ESD Strategy 85
1.14 Summary and Closing Comments 86
Problems 87
References 87
2 Design Synthesis 94
2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 94
2.2 Electrical and Spatial Connectivity 95
2.3 ESD, Latchup, and Noise 96
2.4 Interface Circuits and ESD Elements 98
2.5 ESD Power Clamp Networks 101
2.6 ESD Rail-to-Rail Networks 105
2.7 Guard Rings 109
2.8 Pads, Floating Pads, and No-connect Pads 111
2.9 Structures under Bond Pads 112
2.10 Mixed Signal Architecture: CMOS 112
2.11 MS Architecture: Digital, Analog, and RF Architecture 116
2.12 Digital-to-Analog Interdomain Signal Line Failures 118
2.13 Summary and Closing Comments 124
Problems 124
References 125
3 MOSFET ESD Design 129
3.1 Basic ESD Design Concepts 129
3.2 ESD MOSFET Design: Channel Length 136
3.3 N-Channel MOSFET Design: Channel Width 143
3.4 ESD MOSFET Design: Contacts 144
3.5 ESD MOSFET Design: Metal Distribution 153
3.6 ESD MOSFET Design: Silicide Masking 165
3.7 ESD MOSFET Design: Series Cascode Configurations 170
3.8 ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques 174
3.9 ESD MOSFET Design: Enclosed Drain Design Practice 181
3.10 ESD MOSFET Interconnect Ballasting Design 182
3.11 ESD MOSFET Design: Source and Drain Segmentation 184
3.12 MOSFET Design for Analog Applications 185
3.13 Summary and Closing Comments 187
Problems 187
References 188
4 ESD Design: Diode Design 191
4.1 ESD Diode Design: ESD Basics 191
4.2 ESD Diode Anode Design 194
4.3 ESD Diode Design: Interconnect Wiring 202
4.4 ESD Design: Polysilicon-Bound Diode Designs 210
4.5 N-Well Diode Design 213
4.6 N+/P Substrate Diode Design 216
4.7 ESD Design: Diode String Design 217
4.8 Triple-Well ESD Diode Design 231
4.9 Summary and Closing Comments 234
Problems 234
References 236
5 ESD Design: Passive Resistors 239
5.1 N-Well Resistors 239
5.2 N-Diffusion Resistor Design 248
5.3 P-Diffusion Resistor Design 252
5.4 BR 254
5.5 Summary and Closing Comments 268
Problems 268
References 270
6 Passives for Digital, Analog, and RF Applications 271
6.1 Analog Design Layout Revisited 271
6.2 Common Centroid Design 274
6.3 Interdigitation Design 275
6.4 Common Centroid and Interdigitation Design 276
6.5 Passive Element Design 277
6.6 Resistor Element Design 277
6.7 Capacitor Element Design 283
6.8 Inductor Element Design 283
6.9 Summary and Closing Comments 286
Problems 286
References 286
7 Off-Chip Drivers and ESD 288
7.1 Off-chip Drivers 288
7.2 OCDs: MVI 297
7.3 OCDs: Self-Bias Well OCD Networks 297
7.4 Programmable Impedance OCD Network 302
7.5 OCDs: Universal OCDs 305
7.6 OCDs: Gate-Array OCD Design 306
7.7 OCDs: Gate-Modulated Networks 309
7.8 OCDs ESD Design: Integration of Coupling and Ballasting Techniques 311
7.9 Substrate-Modulated Resistor-Ballasted MOSFET 315
7.10 Summary and Closing Comments 317
Problems 318
References 319
8 Receiver Circuits 322
8.1 Receivers and ESD 322
8.2 Receivers and ESD 324
8.3 Receivers and Receiver Evolution 327
8.4 Receiver Circuits with Pseudozero VT Half-Pass TG 337
8.5 Receiver with ZVT TG 339
8.6 Receiver Circuits with Bleed Transistors 342
8.7 Receiver Circuits with Test Functions 343
8.8 Receiver with Schmitt Trigger Feedback Network 344
8.9 Bipolar Transistor Receivers 347
8.10 Differential Receivers 349
8.11 CMOS Differential Receiver with Analog Layout Concepts 355
8.12 Summary and Closing Comments 363
Problems 364
References 366
9 Silicon on Insulator (SOI) ESD Design 368
9.1 Silicon on Insulator ESD Design Concepts 368
9.2 SOI Design MOSFET with Body Contact: T-Shape Layout Style 372
9.3 SOI Lateral Diode Structure 375
9.4 SOI BR Elements 380
9.5 Dynamic Threshold SOI MOSFET 381
9.6 SOI Dual-Gate MOSFET 384
9.7 SOI ESD Design: Mixed Voltage T-Shape Layout Style 384
9.8 SOI ESD Design: Mixed Voltage Diode Strings 384
9.9 SOI ESD Design: Double-Diode Network 385
9.10 Bulk to SOI ESD Design Remapping 387
9.11 SOI ESD Design in MVI Environments 391
9.12 Comparison of Bulk to SOI ESD Results 393
9.13 SOI ESD Design with Aluminum Interconnects 394
9.14 SOI ESD Design with Copper Interconnects 395
9.15 SOI ESD Design with Gate Circuitry 397
9.16 SOI FinFET Structure 399
9.17 Summary and Closing Comments 403
Problems 403
References 405
10 ESD Circuits: BiCMOS 408
10.1 Bipolar ESD Input Circuits 408
10.2 Diode-Configured Bipolar ESD Input Circuits 412
10.3 Bipolar ESD Input Circuits: Voltage-Triggered Elements 413
10.4 BiCMOS Mixed Signal Designs 437
10.5 Summary and Closing Comments 437
Problems 437
References 438
11 ESD Power Clamps 442
11.1 ESD Power Clamp Design Practices 442
11.2 Design Synthesis of ESD Power Clamps Trigger Networks 446
11.3 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 449
11.4 ESD Power Clamp Issues 452
11.5 ESD Power Clamp Design 453
11.6 Master/Slave ESD Power Clamp Systems 458
11.7 Series-Stacked RC-Triggered ESD Power Clamps 460
11.8 ESD Power Clamps: Triple-Well Series Diodes as Core Clamps 460
11.9 Summary and Closing Comments 464
Problems 465
References 466
12 Bipolar ESD Power Clamps 468
12.1 Bipolar ESD Power Clamps 468
12.2 Bipolar Voltage-Triggered ESD Power Clamps 468
12.3 ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps 473
12.4 Mixed Voltage Interface Forward-Bias Voltage and BVCEO Breakdown Synthesized Bipolar ESD Power Clamps 476
12.5 Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp 480
12.6 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered 485
12.7 Summary and Closing Comments 485
Problems 486
References 487
13 Silicon-Controlled Rectifier Power Clamps 489
13.1 ESD Silicon-Controlled Rectifier Circuits 489
13.2 Lateral Diffused MOS Circuits 492
13.3 DeMOS Circuits 496
13.4 Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits 497
13.5 Summary and Closing Comments 497
Problems 501
References 501
Glossary of Terms 504
Standards 509
Index