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Overview
Content Highlights: Covers the fundamentals of digital logic design and reinforces logic concepts through the design of a MIPS microprocessor. Features side-by-side examples of the two most prominent Hardware Description Languages (HDLs)-Verilog and VHDL-which illustrate and compare the ways each can be used in the design of digital systems. Includes examples throughout the text that enhance the reader's understanding and retention of key concepts and techniques. Companion Web site includes links to CAD tools for FPGA design from Synplicity and Xilinx, lecture slides, laboratory projects, and solutions to exercises.
About the Author:
David Money Harris is an associate professor of engineering at Harvey Mudd College
About the Author:
Sarah L. Harris is an assistant professor of engineering at Harvey Mudd College
Product Details
ISBN-13: | 9780123978165 |
---|---|
Publisher: | Elsevier Science |
Publication date: | 08/24/2012 |
Sold by: | Barnes & Noble |
Format: | eBook |
Pages: | 712 |
Sales rank: | 1,003,114 |
File size: | 15 MB |
Note: | This product may take a few minutes to download. |
About the Author
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing.
Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.
Table of Contents
Preface xvii
Features xviii
Online Supplements xix
How to Use the Software Tools in a Course xix
Labs xx
Bugs xxi
Acknowledgments xxi
From Zero to One 3
The Game Plan 3
The Art of Managing Complexity 4
Abstraction 4
Discipline 5
The Three -Y's 6
The Digital Abstraction 7
Number Systems 9
Decimal Numbers 9
Binary Numbers 9
Hexadecimal Numbers 11
Bytes, Nibbles, and All That Jazz 13
Binary Addition 14
Signed Binary Numbers 15
Logic Gates 19
NOT Gate 20
Buffer 20
AND Gate 20
OR Gate 21
Other Two-Input Gates 21
Multiple-Input Gates 21
Beneath the Digital Abstraction 22
Supply Voltage 22
Logic Levels 22
Noise Margins 23
DC Transfer Characteristics 23
TheStatic Discipline 24
CMOS Transistors 26
Semiconductors 27
Diodes 27
Capacitors 28
nMOS and pMOS Transistors 28
CMOS NOT Gate 31
Other CMOS Logic Gates 31
Transmission Gates 33
Pseudo-nMOS Logic 33
Power Consumption 34
Summary and a Look Ahead 35
Exercises 37
Interview Questions 48
Combinational Logic Design 51
Introduction 51
Boolean Equations 54
Terminology 54
Sum-of-Products Form 54
Product-of-Sums Form 56
Boolean Algebra 56
Axioms 57
Theorems of One Variable 57
Theorems of Several Variables 58
The Truth Behind It All 60
Simplifying Equations 61
From Logic to Gates 62
Multilevel Combinational Logic 65
Hardware Reduction 66
Bubble Pushing 67
X's and Z's, Oh My 69
Illegal Value: X 69
Floating Value: Z 70
Karnaugh Maps 71
Circular Thinking 73
Logic Minimization with K-Maps 73
Don't Cares 77
The Big Picture 78
Combinational Building Blocks 79
Multiplexers 79
Decoders 82
Timing 84
Propagation and Contamination Delay 84
Glitches 88
Summary 91
Exercises 93
Interview Questions 100
Sequential Logic Design 103
Introduction 103
Latches and Flip-Flops 103
SR Latch 105
D Latch 107
D Flip-Plop 108
Register 108
Enabled Flip-Flop 109
Resettable Flip-Flop 110
Transistor-Level Latch and Flip-Flop Designs 110
Putting It All Together 112
Synchronous Logic Design 113
Some Problematic Circuits 113
Synchronous Sequential Circuits 114
Synchronous and Asynchronous Circuits 116
Finite State Machines 117
FSM Design Example 117
State Encodings 123
Moore and Mealy Machines 126
Factoring State Machines 129
FSM Review 132
Timing of Sequential Logic 133
The Dynamic Discipline 134
System Tinting 135
Clock Skew 140
Metastability 143
Synchronizers 144
Derivation of Resolution Time 146
Parallelism 149
Summary 153
Exercises 155
Interview Questions 165
Hardware Description Languages 167
Introduction 167
Modules 167
Language Origins 168
Simulation and Synthesis 169
Combinational Logic 171
Bitwise Operators 171
Comments and White Space 174
Reduction Operators 174
Conditional Assignment 175
Internal Variables 176
Precedence 178
Numbers 179
Z's and X's 179
Bit Swizzling 182
Delays 182
VHDL Libraries and Types 183
Structural Modeling 185
Sequential Logic 190
Registers 190
Resettable Registers 191
Enabled Registers 193
Multiple Registers 194
Latches 195
More Combinational Logic 195
Case Statements 198
If Statements 199
Verilog casez 201
Blocking and Nonblocking Assignments 201
Finite State Machines 206
Parameterized Modules 211
Testbenches 214
Summary 218
Exercises 219
Interview Questions 230
Digital Building Blocks 233
Introduction 233
Arithmetic Circuits 233
Addition 233
Subtraction 240
Comparators 240
ALU 242
Shifters and Rotators 244
Multiplication 246
Division 247
Further Reading 248
Number Systems 249
Fixed-Point Number Systems 249
Floating-Point Number Systems 250
Sequential Building Blocks 254
Counters 254
Shift Registers 255
Memory Arrays 257
Overview 257
Dynamic Random Access Memory 260
Static Random Access Memory 260
Area and Delay 261
Register Files 261
Read Only Memory 262
Logic Using Memory Arrays 264
Memory HDL 264
Logic Arrays 266
Programmable Logic Array 266
Field Programmable Gate Array 268
Array Implementations 273
Summary 274
Exercises 276
Interview Questions 286
Architecture 289
Introduction 289
Assembly Language 290
Instructions 290
Operands: Registers, Memory, and Constants 292
Machine Language 299
R-type Instructions 299
I-type Instructions 301
J-type Instructions 302
Interpreting Machine Language Code 302
The Power of the Stored Program 303
Programming 304
Arithmetic/Logical Instructions 304
Branching 308
Conditional Statements 310
Getting Loopy 311
Arrays 314
Procedure Calls 319
Addressing Modes 327
Lights, Camera, Action: Compiling, Assembling, and Loading 330
The Memory Map 330
Translating and Starting a Program 331
Odds and Ends 336
Pseudoinstructions 336
Exceptions 337
Signed and Unsigned Instructions 338
Floating-Point Instructions 340
Real-World Perspective: IA-32 Architecture 341
IA-32 Registers 342
IA-32 Operands 342
Status Flags 344
IA-32 Instructions 344
IA-32 Instruction Encoding 346
Other IA-32 Peculiarities 348
The Big Picture 349
Summary 349
Exercises 351
Interview Questions 361
Microarchitecture 363
Introduction 363
Architectural State and Instruction Set 363
Design Process 364
MIPS Microarchitectures 366
Performance Analysis 366
Single-Cycle Processor 368
Single-Cycle Datapath 368
Single-Cycle Control 374
More Instructions 377
Performance Analysis 380
Multicycle Processor 381
Multicycle Datapath 382
Multicycle Control 388
More Instructions 395
Performance Analysis 397
Pipelined Processor 401
Pipelined Datapath 404
Pipelined Control 405
Hazards 406
More Instructions 418
Performance Analysis 418
HDL Representation 421
Single-Cycle Processor 422
Generic Building Blocks 426
Testbench 428
Exceptions 431
Advanced Microarchitecture 435
Deep Pipelines 435
Branch Prediction 437
Superscalar Processor 438
Out-of-Order Processor 441
Register Renaming 443
Single Instruction Multiple Data 445
Multithreading 446
Multiprocessors 447
Real-World Perspective: IA-32 Microarchitecture 447
Summary 453
Exercises 455
Interview Questions 461
Memory Systems 463
Introduction 463
Memory System Performance Analysis 467
Caches 468
What Data Is Held in the Cache? 469
How Is the Data Found? 470
What Data Is Replaced? 478
Advanced Cache Design 479
The Evolution of MIPS Caches 483
Virtual Memory 484
Address Translation 486
The Page Table 488
The Translation Lookaside Buffer 490
Memory Protection 491
Replacement Policies 492
Multilevel Page Tables 492
Memory-Mapped I/O 494
Real-World Perspective: IA-32 Memory and I/O Systems 499
IA-32 Cache Systems 499
IA-32 Virtual Memory 501
IA-32 Programmed I/O 502
Summary 502
Exercises 504
Interview Questions 512
Digital System Implementation 515
Introduction 515
74xx Logic 515
Logic Gates 516
Other Functions 516
Programmable Logic 516
PROMs 516
PLAs 520
FPGAs 521
Application-Specific Integrated Circuits 523
Data Sheets 523
Logic Families 529
Packaging and Assembly 531
Transmission lines 534
Matched Termination 536
Open Termination 538
Short Termination 539
Mismatched Termination 539
When to Use Transmission Line Models 542
Proper Transmission Line Terminations 542
Derivation of Z[subscript 0] 544
Derivation of the Reflection Coefficient 545
Putting It All Together 546
Economics 547
MIPS Instructions 551
Further Reading 555
Index 557
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Takes the reader from the fundamentals of digital logic to the actual design of a MIPS microprocessor.