Design of Semiconductor QCA Systems

by Swartzlander, Earl E. Swartzlander Jr.

Overview

Integrated circuits have become smaller, cheaper, and more reliable, and certainly have revolutionized the world of electronics. Integrated circuits are used in almost all electronic devices and systems, many of which-such as the Internet, computers, and mobile phones-have become essential parts of modern life and have changed the way we live. Quantum-dot cellular automata (QCA) provides a revolutionary approach to computing with a new form of device-to-device interactions. The design of a QCA circuit is radically different from a conventional digital design due to its unique characteristics at both the physical level and logic level. This book focuses on the logic- and algorithmic-level design. Research on both circuit architecture and device design is required for a profound understanding of QCA nanotechnologies. This detailed reference presents practical design aspects of QCA with an emphasis on developing real-world implementations. The authors provide excellent analysis on QCA designs and provide metrics on how to compare different designs based on their area, power consumption, and timing.

Product Details

ISBN-13:	9781608076871
Publisher:	Artech House, Incorporated
Publication date:	09/30/2013
Pages:	242
Product dimensions:	6.20(w) x 9.20(h) x 0.80(d)

Table of Contents

Part I QCA Background 1

1 Introduction 3

1.1 Motivation 4

1.2 Contributions 5

1.3 Book Outline 7

References 8

2 Quantum-dot Cellular Automata 11

2.1 QCA Fundamentals 12

2.1.1 QCA Cells and Wires 12

2.1.2 QCA Basic Gates 13

2.1.3 QCA Wire Crossings 14

2.2 Physical Implementations of QCA 15

2.2.1 Metal-Island QCA 16

2.2.2 Semiconductor QCA 16

2.2.3 Molecular QCA 16

2.2.4 Magnetic QCA 17

2.3 Clocking Schemes 17

2.3.1 Typical Four-Phase Clocking 17

2.3.2 Clocking Floorplans 19

2.3.3 Clocking for Reversible Computing 20

2.4 Design and Simulation Tools 20

2.4.1 QCADesigner 21

2.4.2 QCAPro 25

2.5 Research Into QCA Digital Design 25

2.5.1 Computer Arithmetic Circuits 26

2.5.2 Combinational Circuits 27

2.5.3 Latches and Sequential Circuits 27

2.5.4 Memory Design 28

2.5.5 General and Specific Processors 28

2.5.6 Design Methods and Design Automation 28

2.5.7 Testing, Defects and Faults 29

2.6 Basic Design Rules 30

2.6.1 Layout Rules 30

2.6.2 Timing Rules 33

2.7 Summary 34

References 34

Part II OCA Arithmetic Circuits 45

3 QCA Adders 47

3.1 Introduction 47

3.2 Ripple Carry Adder 47

3.2.1 Architectural Design 47

3.2.2 Schematic Design 48

3.2.3 Layout Design 48

3.3 Carry Lookahead Adder 48

3.3.1 Architectural Design 48

3.3.2 Schematic Design 51

3.3.3 Layout Design 54

3.3.4 Simulation Results 54

3.4 Conditional Sum Adder 54

3.4.1 Architectural Design 54

3.4.2 Schematic Design 55

3.4.3 Layout Design 60

3.5 Comparison of the Conventional Adders 60

3.6 Carry Flow Adder 64

3.6.1 Basic Design Approach 64

3.6.2 Carry Flow Full Adder Design 66

3.6.3 Simulation Results 67

3.7 Decimal Adder 69

3.7.1 Conventional BCD Adder 70

3.7.2 Carry Lookahead Decimal Adder 73

3.7.3 Comparison and Analysis 77

3.8 Conclusion 80

References 80

4 QCA Multipliers 83

4.1 Introduction 83

4.2 QCA Array Multipliers 84

4.2.1 Structural Design 84

4.2.2 Schematic Design 84

4.2.3 Implementation of Array Multipliers with QCAs 85

4.3 Wallace and Dadda Multipliers For QCA 88

4.3.1 Introduction 88

4.3.2 Schematic Design 89

4.3.3 Implementation with QCAs 92

4.4 Quasi-Modular Multipliers For QCA 94

4.4.1 Quasi-Modular Multiplier Method 94

4.4.2 Structural Design 97

4.4.3 Implementation with QCAs 98

4.4.4 Simulation Results 98

4.5 Comparison of QCA Multipliers 102

4.6 Conclusion 103

References 103

5 QCA Dividers 105

5.1 Introduction 105

5.2 Digit Recurrent Divider 105

5.2.1 Types of Digit Recurrent Dividers 105

5.2.2 Conventional Restoring Binary Divider Architecture 106

5.2.3 Restoring Binary Divider 106

5.2.4 Implementation of the Restoring Divider 109

5.2.5 Simulation Results 111

5.3 Convergent Divider 112

5.3.1 The Goldschmidt Division Algorithm 115

5.3.2 The Data Tag Method for Iterative Computation 116

5.3.3 Implementation of the Goldschmidt Divider 119

5.3.4 Simulation Results 127

5.4 Conclusion 131

References 131

Part III QCA Design Methodologies 135

6 Design of QCA Circuits Using Cut-Set Retiming 137

6.1 Introduction 137

6.2 QCA Timing Constraints and Timing Issues 138

6.2.1 Timing Constraint I 138

6.2.2 Timing Constraint II 139

6.2.3 Timing Issues in QCA 139

6.3 Data Flow Graph and Retiming Technique 141

6.3.1 Data Flow Graph 141

6.3.2 Mapping CMOS DFG to QCA DFG 142

6.3.3 Retiming Technique 143

6.4 A Cut-Set Retiming Design Procedure 143

6.4.1 Cut-Set Retiming and Its Rules 143

6.4.2 Proposed Cut-Set Retiming Design Procedure 145

6.5 Case Studies 148

6.5.1 MMM Design 148

6.5.2 S27 Benchmark Circuit Design 154

6.6 Conclusion 160

References 162

7 QCA Systolic Array Design 165

7.1 Introduction 165

7.2 Signal Flow Graph and Systolic Array Architecture 166

7.2.1 Signal Flow Graph 166

7.2.2 Systolic Array Architecture 166

7.3 Case Study I: Matrix Multiplier 167

7.3.1 Systolic Array Matrix Multiplier Introduction 167

7.3.2 QCA Systolic Matrix Multiplier Design 168

7.3.3 Design Study 174

7.4 Case Study II: Galois Field Multiplier 181

7.4.1 Galois Field Multiplier Introduction 181

7.4.2 QCA Systolic Galois Field Multiplier Design 183

7.4.3 QCA Single Processor Galois Field Multiplier Design 187

7.4.4 Design Study 190

7.5 QCA Systolic Array Design Methodology 192

7.6 Conclusion 193

References 193

8 Evaluation of QCA Circuits with New Cost Functions 195

8.1 Introduction 195

8.2 QCA Cost Metrics and Cost Functions 196

8.2.1 Area/Complexity 198

8.2.2 Delay 198

8.2.3 Irreversible Power Dissipation 199

8.2.4 Number of Crossovers 199

8.2.5 Proposed QCA Cost Functions 200

8.3 Overview of QCA Adders 201

8.3.1 Coplanar Adders 201

8.3.2 Multilayer Adders 205

8.4 Comparison of QCA Adders with Proposed Cost Functions 212

8.4.1 Comparison with Individual Metrics 213

8.4.2 Comparison with QCA Cost Function I 215

8.4.3 Comparison with QCA Cost Function II 217

8.4.4 Discussion 219

8.5 Conclusion 220

References 220

9 Conclusion and Future Work 225

9.1 Conclusion 225

9.2 Future Work 227

9.2.1 QCA Design Automation Tools 228

9.2.2 Finite State Machine Design 228

9.2.3 Reversible Circuit Design 228

9.2.4 Decimal Arithmetic 228

References 229

About the Authors 231

Index 235